As it is well known, the development of the electric features of PC, WORKSTATION and SERVER processors obliges manufactures to look for new approaches to meet the requirements imposed by corresponding central processing units, commonly called CPUs: high supply voltage precision, particularly +/−0.8% in the steady state condition and +/−3% in the transient condition. Nevertheless supply voltages fall to 1.1V, load currents increase up to 100 A with fronts of 100 A/μs and an efficiency being higher than 80% is required. In this perspective, it is thus known to use a voltage regulator module, hereafter simply indicated with module VRM, associated to each microprocessor in each SERVER or WORKSTATION.
Aiming at increasing performances and ensuring the integrity of the whole system wherein operation occurs, it is also known to use several modules VRM, connected in parallel and having all input supply terminals connected to each other and all output voltage terminals connected to each other, thus forming a single multi-module supply unit.
But such a parallel architecture requires a convenient distribution control of the currents flowing in parallel modules VRM, in order to allow the total load current to be equitably distributed among the modules, i.e. that each module VRM carries a current corresponding to the current required at the output split by the number of modules.
A known control technique being used to reach this aim is the so-called current sharing technique. This technique exploits a current sharing bus, common to all modules VRM of an architecture, suitable to provide the signals required by each module VRM in order to change the output current thereof, in order to make it equal to the current of the other modules connected thereto. This Current Sharing Bus will be briefly indicated hereafter with “CSB”.
Several methods are known in the art to control the CSB and the relevant current sharing outputted by the N modules connected thereto. A first known method to control the CSB operates at the system level, i.e. for all architecture modules and it is known as Average Program (AP) control. This method is based on the comparison between the average current delivered by the N modules VRM and the current delivered by a single module. This method is described for example in the U.S. Pat. application No. 2002/0073347 A1 dated Jun. 13, 2002, in the name of the same applicant.
The corresponding circuit is implemented using discrete components and it is shown in FIG. 1, in the particular case of a multi-module architecture 1 having a parallel configuration of only two modules 2, indicated with VRM1 and VRM2. Each module 2 has an input terminal IN receiving a same input voltage signal VIN, it outputs a single current Ii [i=1,2] and it has an output terminal in common with the other modules, in correspondence with an output node OUT wherein an output signal VOUT occurs. The sum IOUT of the currents Ii is a current value generated by the multi-module architecture 1.
In particular, a first module VRM1 comprises two operational amplifiers OP1 and OP2 with respective inverting terminals N1 and N2, and non-inverting terminals P1 and P2. This first module VRM1 also comprises a PWM signal generator, indicated with PWM1 receiving the input signal VIN and a signal U1 outputted by the amplifier OP1. The generator PWM1 is output-connected to the inverting terminal N1 of the operational amplifier OP1, by means of the node X1, and to the inverting terminal N2 of the operational amplifier OP2, by means of the node X2. A reference voltage VREF1 is added to an output signal U2 of the operational amplifier OP2 in an adder node S1, connected to the non-inverting terminal P1 of the operational amplifier OP1.
The multi-module architecture 1 of FIG. 1 also comprises a second module VRM2, structurally identical to the first module VRM1. In particular, the second module VRM2 has a PWM signal generator, indicated with PWM2, two operational amplifiers OP3 and OP4 with respective inverting terminals N3 and N4 and non-inverting terminals P3, P4, two circuit nodes X3, X4 and an adder node S2.
The non-inverting terminal P2 of the operational amplifier OP2 of the first module VRM1 is connected to the non-inverting terminal P4 of the operational amplifier OP4 of the second module VRM2, by means of the CSB. In the first module VRM1, a resistor R1 is interposed between the node X2 and the CSB. In the second module VRM2, a resistance R2 is interposed between the node X4 and the CSB. In this node the CBS has a voltage VCSB corresponding to the average of the currents I1 and I2 delivered by the modules VRM1 and VRM2.
Therefore it results that the current value IOUT outputted by the output terminal OUT of the multi-module architecture 1 is given by the sum of the currents I1 and I2 outputted by the single modules. Moreover, the common voltage Vout of the output terminal OUT of the multi-module architecture 1 is equal to Vout.
The Average Program control method, implemented by the multi-module architecture 1, allows a completely linear and accurate regulation of the currents Ii delivered by each module comprised therein to be obtained.
Although advantageous under several aspects, this embodiment has several drawbacks, particularly when one or more modules VRM enter a fault condition. The CSB detects a lower current than the one required by a load connected to the architecture 1 and thus the current sharing control fails.
FIG. 2 shows a detail of the circuit of FIG. 1, enlarged to N parallel modules VRM, wherein one of the modules, particularly a first module VRM1 is supposed to enter a FAULT condition.
In this situation, the CSB voltage is given by:
      V    CSB    =                    0        +                  I          2                +                  I          3                +        …        +                  I          N                    N        *    R  the current I1 of the module VRM1, which is supposed to be in the FAULT condition, being void and not contributing to the VCSB computing. The resulting voltage VCSB is thus lower than the one required by the load with a subsequent failure of the current sharing control performed by the multi-module architecture 1.
The only approach remaining open to avoid this problem is to release the module in FAULT from the architecture, by inserting between the CSB and the module itself a switch SW, controlled by a signal, monitoring the correct operation of each module. The switch SW is inserted between the operational amplifier OP2 and the CSB and it is controlled by a control signal generated by a failure detection block 3.
To manage the failure conditions or fault, each module VRMi is then associated to a switch Swi (i=1 . . n). The detail of a module VRM with a switch SW is shown in FIG. 3 wherein, to identify components corresponding to the ones shown in FIG. 1, the same reference labels have been used.
The insertion of this switch SWi ensures the current sharing control, but it also involves an increase in the area occupation on the board wherein the module VRM is integrated, with a subsequent increase in the application cost, making the use thereof unprofitable.
Other known methods to control the CSB use embodiments being integrated in each single module VRM and they are known as active CSB control methods. These active CSB methods, integrated at the single module level, generally use Master & Slave architectures.
An embodiment of a first Master & Slave architecture for the active CSB control, so-called “Direct Master” (DM), is schematically shown in FIG. 4 and globally indicated with 4. In particular, by using this type of architecture 4, one of the modules VRM acts as a reference module. As it has been seen for the multi-module architecture 1, the multi-module architecture 4 also comprises several modules VRM connected to each other between an input terminal IN and an output terminal OUT. In particular, the input terminal IN receives a common input voltage signal VIN, and the output terminal OUT a common output signal VOUT. An output current Ii is outputted by each module whose sum IOUT is the current value generated by the multi-module architecture 4.
FIG. 4 particularly shows a parallel configuration of only two modules VRM3 and VRM4, configured according to a direct master architecture, having a first module VRM3 acting as a reference module. The first module VRM3 thus comprises an operational amplifier OP5 having an inverting terminal N5 and a non-inverting terminal P5. This first module VRM3 also comprises a signal generator PWM3 receiving the input signal VIN, and a signal U5 outputted by the amplifier OP5. The inverting terminal N5 of the operational amplifier OP5 is connected to the generator PWM3, by means of a node X5, while the non-inverting terminal P5 of the operational amplifier OP5 is connected to a first reference voltage VREF1.
The multi-module architecture 4 also comprises a second module VRM4 comprising an error amplifier OP6 and a sharing regulation amplifier OP7 having respective inverting N6 and N7 and non-inverting P6 and P7 terminals. This second module VRM4 also comprises a signal generator PWM4 receiving the input signal VIN, and a signal U6 outputted by the error amplifier OP6. The signal generator PWM4 is output-connected to the inverting terminal N6 of the error amplifier OP6 and to the inverting terminal N7 of the sharing regulation amplifier OP7 by means of a node X6. A second reference voltage VREF2 is added to an output signal U7 of the sharing regulation amplifier OP7 in an adder node S3 connected to the non-inverting terminal P6 of the error amplifier OP6. The non-inverting terminal P7 is connected to the node X5 by means of the CSB.
The multi-module architecture 4 differs from the architecture 1 of FIG. 1 by the structure of the respective first modules VRM1 and VRM3. The first module VRM3 is a master module and it controls the CSB, providing a current reference signal I3 to all the other architecture modules. This approach has the advantage of being simple to realize and of ensuring a linear regulation.
Unfortunately, also this approach has a major drawback. In fact, in case of fault of the first master module VRM3, also the remaining modules VRM enter the FAULT condition, making the current sharing control fail and turning the whole architecture off. To solve this problem, it is possible to use an alternative embodiment of the multi-module architecture being so-called Automatic Master (AM). In this architecture, the module VRM with the highest delivered current acts as a master and it controls the CSB, so that the remaining modules behave as Slaves.
An example of this architecture is shown in FIG. 5, globally indicated with 5, wherein, to identify components corresponding to the ones shown in FIG. 4, the same reference labels have been used. As shown in FIG. 5, the first module VRM3 comprises a first diode D1 inserted between the output terminal thereof and the CSB. Therefore, the first diode D1 is thus interposed between the node X5 and the non-inverting terminal P7 of the sharing regulation amplifier OP7. Similarly, the second module VRM4 comprises a second diode D2 inserted between the CSB and the output terminal thereof. In particular, the second diode D2 connects the node X6 to the non-inverting terminal P7 of the sharing regulation amplifier OP7 of the second module VRM4. The two diodes D1 and D2 are generally realized by means of operational amplifiers in the “Super-Diode” configuration.
In case of “FAULT” of a module VRM, the current of this module is void, and the corresponding diode is reverse biased causing an automatic release of the module from the CSB control which is continuously driver by a Master module, i.e. the module having the highest output current. Therefore, the problem of a module Fault in a master & slave configuration is solved.
But also this approach has some drawbacks just caused by the presence of diodes D1 and D2. In fact, a known major problem affecting this type of architecture is indicated with the term “chattering” and it includes the lack of stabilization of the module current which keeps on oscillating around the working point as shown in FIG. 6 because of the diodes. The current of each module oscillates at a frequency and at an oscillation amplitude being determined by the CSB band and the loop gain respectively. The CSB loop comprising the sharing regulation amplifier OP7, the error amplifier OP6 and the signal generator PWM4.
To remove the “Chattering” problem it is necessary to insert an offset generator between the “Master” module and the “Slave” modules, as schematically shown in FIG. 7. In particular, this figure shows a multi-module architecture 7 of the Automatic Master with offset type, wherein an offset generator OFS is inserted between the non-inverting terminal P7 of the sharing regulation operational amplifier OP7 of the second module VRM2 or slave module and the node X6. The first module VRM3 or master module VRM generates a current Io_master, while the slave module VRM4 generates a current Io_slave. The trend in time of the two currents is shown in FIG. 8.
But it should be noted that the insertion of the offset generator makes a higher tolerance for the currents delivered by the modules necessary, with a subsequent worsening of the control precision, realized by the multi-module architecture 7.
FIG. 9 shows a possible implementation on an integrated circuit of an Automatic Master active CSB architecture equipped with four PINs for the external components. This implementation is described in the U.S. Pat. No. 6,642,631 B1 of the Applicant, published on Nov. 4, 2003. In FIG. 9, the master module VRM4 of FIG. 7 is regulated by a control circuit 9. This circuit comprises a sensing current amplifier OP8 in cascade with a sharing bus amplifier OP9. The sensing current amplifier OP8 is connected by means of its non-inverting terminal P8 to a reference voltage value Vref and, by means of the inverting terminal N8 to a current generator ISENSE by means of a circuit node NFB (first PIN).
A resistor RSHARE1 is outside the circuit 9, playing the role of programming the highest CSB current value. This resistor RSHARE1 is connected to the circuit node NFB as well as to a node NOUT (second PIN) connected in turn to an output node X8 of the sensing current amplifier OP8 and to a controlled circuit 10, substantially corresponding to the master module VRM4 of FIG. 7. In the control circuit 10, to identify components being equal or similar to the ones of the master module VRM4, the same reference numbers will be used. The node NFB is connected by means of the offset generator OFS to the inverting terminal N7 of the sharing regulation amplifier OP7.
The node X8 is connected to the non-inverting terminal P9 of the sharing bus amplifier OP9. The inverting terminal N9 of this amplifier is connected to a circuit node X9, connected in turn to a node NCSB (third PIN) as well as to a circuit node X10 being interposed between the diode D2, which allows the conduction of the signal outputted by the sharing bus amplifier OP9, and the non-inverting terminal P7 of the sharing regulation amplifier OP7. The sharing regulation amplifier OP7 has an output U7 connected to the error amplifier OP6, shown in FIG. 4, but not shown in FIG. 9.
A similar approach to the one shown in FIG. 9 is shown in FIG. 10 and it shows the case wherein the signal coming from the current sense is already a voltage signal. In this figure a resistor RSHARE2 has been thus added, being coupled to the already-existing resistor RSHARE1 connected to a ground supply voltage GND, the rest of the circuit being unchanged.
The implementation on an integrated circuit of the Automatic Master active CSB architecture described in the two FIGS. 9 and 10 thus requires the use of as much as four pins, identified by the nodes NFB, IOUT, NCSB e NSHARE, to be coupled to the external components, and as much as three operational amplifiers OP7, OP8, OP9 as well as an external resistor RSHARE1, being capable to program the CSB threshold. It has also a systematic error on the current sharing between the modules due to the insertion of the offset generator OFS, being necessary to remove the chattering problem of the current Ii delivered by the different modules VRM. This implementation, although not being simple to realize and although having evident limitations and drawbacks, is the only integrated solution presently available in the market, known with the name of ON Semiconductor CS5305.
The technical problem underlying the present invention is to provide a CSB control circuit having such structural and functional features as to allow the total load current to be equitably distributed among the modules VRM, overcoming the limitations and/or drawbacks still penalizing the prior art embodiments.